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30 v, 8 mhz, low bias current, single-supply, rro, precision op amps data sheet ada4622-1 / ada4622-2 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015C2017 analog devices, inc. all rights reserved. technical support www.analog.com features next generation of the ad820 / ad822 wide gain bandwidth product: 8 mhz typical high slew rate: +23 v/s/?18 v/s typical low input bias current: 10 pa maximum at t a = 25c low offset voltage a grade: 0.8 mv maximum at t a = 25c b grade: 0.35 mv maximum at t a = 25c low offset voltage drift a grade: 2 v/c typical, 15 v/c maximum b grade: 2 v/c typi cal, 5 v/c maximum input voltage range includes pin v? rail-to-rail output electromagnetic interference rejection ratio (emirr) 90 db typical at f = 1000 mhz and f = 2400 mhz industry-standard package and pinouts applications high output impedance sensor interfaces photodiode sensor interfaces transimpedance amplifiers adc drivers precision filters and signal conditioning pin configurations 13502-401 1 2 3 4 8 7 6 5 ada4622-1 top view (not to scale) ?in +in v? nic notes 1. nic = not interna l ly connected. v+ out nic disable figure 1. 8-lead soic pin configuration, ada4622-1 (see the pin configurations and function descri ptions section for additional pin configurations) 1 2 3 4 ?in a +in a v? out a 8 7 6 5 out b ?in b +in b v+ 13502-001 ada4622-2 (not to scale) top view figure 2. 8-lead msop pin configuration, ada4622-2 (see the pin configurations and function descri ptions section for additional pin configurations) general description the ada4622-1 / ada4622-2 are the next generation of the ad820 and the ad822 single-supply, rail-to-rail output (rro), precision junction field effect transistors (jfet) input op amps. the ada4622-1 / ada4622-2 include many improvements that make them desirable as an upgrade without compromising the flexibility and ease of use that makes the ad820 and the ad822 useful for a wide variety of applications. the input voltage range includes the negative supply and the output swings rail-to-rail. input emi filters increase the signal robustness in the face of closely located switching noise sources. the speed, in terms of bandwidth and slew rate, increases along with a strong output drive to improve settling time performance and enable the devices to drive the inputs of modern single-ended, successive approximation register (sar) analog-to-digital converters (adcs). voltage noise is reduced; while keeping the supply current the same as the ad820 and the ad822 , broadband noise is reduced by 25%, and 1/f is reduced by half. dc precision in the ada4622-1 / ada4622-2 improved from the ad820 and the ad822 with half the offset and a maximum thermal drift specification added to the ada4622-1 / ada4622-2 . the common-mode rejection ratio (cmrr) is improved from the ad820 and the ad822 to make the ada4622-1 / ada4622-2 more suitable when used in noninverting gain and difference amplifier configurations. the ada4622-1 / ada4622-2 are specified for operation over the extended industrial temperature range of ?40c to +125c and operates from 5 v to 30 v with specifications at +5 v, 5 v, and 15 v. the ada4622-1 is available in a 5-lead sot-23 package and an 8-lead lfcsp package, and the ada4622-2 is available in an 8-lead soic package, an 8-lead msop package, and an 8-lead lfcsp package.
ada4622-1/ada4622-2 data sheet rev. b | page 2 of 34 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin configurations ........................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics, v sy = 15 v ...................................... 3 ? electrical characteristics, v sy = 5 v ........................................ 5 ? electrical characteristics, v sy = 5 v .......................................... 7 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? typical performance characteristics ........................................... 12 ? theory of operation ..................................................................... 24 ? input characteristics .................................................................. 24 ? output characteristics............................................................... 25 ? shutdown operation .................................................................. 26 ? applications information .............................................................. 27 ? recommended power solution ................................................ 27 ? maximum power dissipation ................................................... 27 ? second-order low-pass filter.................................................. 27 ? wideband photodiode preamplifier ........................................ 27 ? peak detector .............................................................................. 30 ? multiplexing inputs .................................................................... 30 ? full wave rectifier ..................................................................... 31 ? outline dimensions ....................................................................... 32 ? ordering guide .......................................................................... 34 ? revision history 2/2017rev. a to rev. b added ada4622-1 ........................................................ throughout changed ad822 to ad820/ad822 ............................ throughout changed ada4622-2 to ada4622-1/ada4622-2 .. throughout changed 7.5 mhz to 8 mhz in product title .............................. 1 added figure 1; renumbered sequentially .................................. 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to table 3 ............................................................................ 7 changes to table 5 ............................................................................ 9 added figure 3, table 6, figure 4, and table 7; renumbered sequentially ..................................................................................... 10 changes to figure 11 and figure 12 ............................................. 12 added figure 13 .............................................................................. 12 added figure 78 .............................................................................. 23 added shutdown operation and figure 86 to figure 89 .......... 26 added multiplexing inputs section, figure 99, and figure 100 ..... 30 added full wave rectifier section, figure 101, and figure 102 .... 31 updated outline dimensions ....................................................... 32 change to ordering guide ............................................................ 34 2/2016rev. 0 to rev. a added 8-lead lfcsp ......................................................... universal changes to general description section ....................................... 1 changes to settling time to 0.1% parameter and settling time to 0.01% parameter, table 1 ............................................................. 4 changes to table 5 ............................................................................. 9 added pin configurations and function descriptions section, figure 2, figure 3, table 6, figure 4, and table 7; renumbered sequentially ..................................................................................... 10 changes to figure 9 ........................................................................ 11 changes to input characteristics section ................................... 23 changes to recommended power solution section ................. 25 changes to wideband photodiode preamplifier section ......... 26 change to figure 85 ....................................................................... 26 change to figure 86 ....................................................................... 27 updated outline dimensions ....................................................... 29 changes to ordering guide .......................................................... 30 10/2015revision 0: initial version
data sheet ada4622- 1/ada4622 - 2 rev. b | page 3 of 34 specifications electrical character istics , v sy = 15 v supply voltage ( v sy ) = 1 5 v, common - mode voltage ( v cm ) = output voltage ( v out ) = 0 v , t a = 25c, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os a grade + 0.04 0.8 mv ?40c < t a < +125c 2 mv b grade +0.04 0.35 mv ada4622 -1 ?40c < t a < +125c 1 mv ada4622 -2 ?40c < t a < +125c 0.8 mv offset voltage match 1 mv offset voltage drift v os /t a grade ?40c < t a < +125c 2 15 v/c b grade ?40c < t a < +125c 2 5 v/c input bias current i b + 2 10 pa ?40c < t a < +125c 1.5 na v cm = ?15 v ?15 pa input offset current i os 10 pa ?40c < t a < +125c 0.5 na input voltage range ivr ?15.2 +14 v common - mode rejection ratio cmrr a grade v cm = ?15 v to +12 v 84 100 db ?40c < t a < +125c 81 db b grade v cm = ?15 v to +12 v 87 100 db ?40c < t a < +125c 85 db large signal voltage gain a vo r l = 10 k?, v out = ?14.5 v to +14.5 v 117 122 db ?40c < t a < +125c 109 db r l = 1 k?, v out = ?14 v to +14 v 102 110 db ?40c < t a < +125c 93 db input capacitance c indm differential mode 0.4 pf c incm common mode 3.6 pf input resistance r diff differential mode 10 13 ? r cm common mode 10 13 ? output characteristics output voltage high v oh i source = 1 ma 14.95 14.97 v ?40c < t a < +125c 14.9 v i source = 15 ma 14.3 14.5 v ?40c < t a < +125c 14.1 v low v ol i sink = 1 ma ? 14.955 ? 14.935 v ?40c < t a < +125c ? 14.88 v i sink = 15 ma ? 14.685 ? 14.55 v ?40c < t a < +125c ? 14.25 v output current i out v dropout < 1 v 20 ma short - circuit current i sc sourcing 42 ma sinking ?51 ma closed - loop output impedance z out f = 1 khz, gain (a v ) = 1 0.1 ? a v = 10 0.4 ? a v = 100 3 ?
ada4622- 1/ada4622 - 2 data sheet rev. b | page 4 of 34 parameter symbol test conditions/comments min typ max unit power supply power supply rejection ratio psrr v sy = 4 v to 18 v 87 103 db ?40c < t a < +125c 81 db supply current per amplifier i sy ada4622 - 1 715 750 a ?40c < t a < +125c 775 a ada4622 -2 665 700 a ?40c < t a < +125c 725 a shutdown current ada4622 -1 only 60 a dynamic performance slew rate sr v out = 12.5 v, r l = 2 k?, load capacitor (c l ) = 100 pf, a v = 1 low to high transition 23 v/s high to low transition ?18 v/s gain bandwidth product gbp a v = 100, c l = 35 pf 8 mhz unity - gain crossover ugc a v = 1 7 mhz ?3 db bandwidth ?3 db a v = 1 15.5 mhz phase margin m 53 degrees settling time t s input voltage (v in ) = 10 v step, r l = 2 k ? , c l = 15 pf, a v = ?1 t o 0.1% 1.5 s t o 0.01% 2 s emi rejection ratio emirr v in = 100 mv p -p f = 1000 mhz 90 db f = 2400 mhz 90 db noise performance voltage noise e n p -p 0.1 hz to 10 hz 0.75 v p -p voltage noise density e n f = 10 hz 30 nv/hz f = 100 hz 15 nv/hz f = 1 khz 12.5 nv/hz f = 10 khz 12 nv/hz current noise density i n f = 1 khz 0.8 fa/hz total harmonic distortion + noise thd + n a v = 1, f = 10 hz to 20 khz, v in = 7 v rms at 1 khz bandwidth (bw) = 80 khz 0.0003 % bw = 500 khz 0.00035 % matching specifications maximum offset voltage over temperature 0.5 mv offset voltage temperature drift 2.5 v/c input bias current 0.5 5 p a crosstalk c s r l = 5 k ? , v in = 20 v p -p f = 1 khz ?112 db f = 100 khz ?72 db
data sheet ada4622- 1/ada4622 - 2 rev. b | page 5 of 34 electrical character istics , v sy = 5 v v sy = 5 v, v cm = v out = 0 v , t a = 25c, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os a grade + 0.04 0.8 mv ?40c < t a < +125c 2 mv b grade +0.04 0.35 mv ada4622 -1 ?40c < t a < +125c 1 mv ada4622 -2 ?40c < t a < +125c 0.8 mv offset voltage match 1 mv offset voltage drift v os /t a grade ?40c < t a < +125c 2 15 v/c b grade ?40c < t a < +125c 2 5 v/c input bias current i b +2 10 pa ?40c < t a < +125c 1.5 na v cm = v? ?5 pa input offset current i os 10 pa ?40c < t a < +125c 0.5 na input voltage range ivr ?5.2 +4 v common - mode rejection ratio cmrr a grade v cm = ? 5 v to +2 v 75 91 db ?40c < t a < +125c 73 db b grade v cm = ? 5 v to +2 v 78 91 db ?40c < t a < +125c 75 db large signal voltage gain a vo r l = 10 k ? , v out = ?4.4 v to +4.4 v 113 118 db ?40c < t a < +125c 105 db r l = 1 k ? , v out = ?4.4 v to +4.4 v 100 105 db ?40c < t a < +125c 91 db input capacitance c indm differential mode 0.4 pf c incm common mode 3.6 pf input resistance r diff differential mode 10 13 ? r cm common mode 10 13 ? output characteristics output voltage high v oh i source = 1 ma 4.95 4.97 v ?40c < t a < +125c 4.9 v i source = 15 ma 4.3 4.51 v ?40c < t a < +125c 4.1 v low v ol i sink = 1 ma ? 4.955 ? 4.935 v ?40c < t a < +125c ? 4.88 v i sink = 15 ma ? 4.685 ? 4.55 v ?40c < t a < +125c ? 4.25 v output current i out v dropout < 1 v 20 ma short - circuit current i sc sourcing 31 ma sinking ?40 ma closed - loop output impedance z out f = 1 khz, a v = 1 0.1 ? a v = 10 0.4 ? a v = 100 4 ?
ada4622- 1/ada4622 - 2 data sheet rev. b | page 6 of 34 parameter symbol test conditions/comments min typ max unit power supply power supply rejection ratio psrr v sy = 4 v to 18 v 87 103 db ?40c < t a < +125c 81 db supply current per amplifier i sy ada4622 - 1 660 725 a ?40c < t a < +125c 750 a ada4622 -2 610 675 a ?40c < t a < +125c 700 a shutdown current ada4622 -1 only 50 a dynamic performance slew rate sr v out = 3 v, r l = 2 k?, c l = 100 pf, a v = 1 low to high transition 21 v/s high to low transition ?16 v/s gain bandwidth product gbp a v = 100, c l = 35 pf 7.8 mhz unity - gain crossover ugc a v = 1 6.5 mhz ?3 db bandwidth ?3 db a v = 1 10 mhz phase margin m 50 degrees settling time t s v in = 8 v step, r l = 2 k ? , c l = 15 pf, a v = ?1 to 0.1% 1.5 s to 0.01% 2 s emi rejection ratio emirr v in = 100 mv p -p f = 1000 mhz 90 db f = 2400 mhz 90 db noise performance voltage noise e n p -p 0.1 hz to 10 hz 0.75 v p -p voltage noise density e n f = 10 hz 30 nv/hz f = 100 hz 15 nv/hz f = 1 khz 12.5 nv/hz f = 10 khz 12 nv/hz current noise density i n f = 1 khz 0.8 pa/hz total harmonic distortion + noise thd + n a v = 1, f = 10 hz to 20 khz, v in = 1.5 v rms at 1 khz bw = 80 khz 0.0005 % bw = 500 khz 0.0008 % matching specifications maximum offset voltage over temperature 0.5 mv offset voltage temperature drift 2.5 v/c input bias current 0.5 5 pa crosstalk c s r l = 5 k ? , v in = 6 v p -p f = 1 khz ?112 db f = 100 khz ?72 db
data sheet ada4622- 1/ada4622 - 2 rev. b | page 7 of 34 electrical character istics , v sy = 5 v v sy = 5 v, v cm = 0 v, v out = v sy /2, t a = 25 c, unless otherwise noted. table 3 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os a grade + 0.04 0.8 mv ?40c < t a < +125c 2 mv b grade +0.04 0.35 mv ada4622 -1 ?40c < t a < +125c 1 mv ada4622 -2 ?40c < t a < +125c 0.8 mv offset voltage match 1 mv offset voltage drift v os /t a grade ?40c < t a < +125c 2 15 v/c b grade ?40c < t a < +125c 2 5 v/c input bias current i b 2 10 pa ?40c < t a < +125c 1.5 na input offset current i os 10 pa ?40c < t a < +125c 0.5 na input voltage range ivr ?0.2 +4 v common - mode rejection ratio cmrr a grade v cm = 0 v to 2 v 70 87 db ?40c < t a < +125c 67 db b grade v cm = 0 v to 2 v 73 87 db ?40c < t a < +125c 70 db large signal voltage gain a vo r l = 10 k ? to v?, v out = 0.2 v to 4.6 v 110 115 db ?40c < t a < +125c 99 db r l = 1 k ? to v?, v out = 0.2 v to 4.6 v 96 104 db ?40c < t a < +125c 87 db input capacitance c indm differential mode 0.4 pf c incm common mode 3.6 pf input resistance r diff differential mode 10 13 ? r cm common mode 10 13 ? output characteristics output voltage high v oh i source = 1 ma 4.95 4.97 v ?40c < t a < +125c 4.9 v i source = 15 ma 4.3 4.5 v ?40c < t a < +125c 4.1 v low v ol i sink = 1 ma ? 14.955 ? 14.935 v ?40c < t a < +125c ? 14.88 v i sink = 15 ma ? 14.69 ? 14.55 v ?40c < t a < +125c ? 14.25 v output current i out v dropout < 1 v 20 ma short - circuit current i sc sourcing 27 ma sinking ?35 ma closed - loop output impedance z out f = 1 khz, a v = 1 0.1 ? a v = 10 0.6 ? a v = 100 5 ?
ada4622- 1/ada4622 - 2 data sheet rev. b | page 8 of 34 parameter symbol test conditions/comments min typ max unit power supply power supply rejection ratio psrr v sy = 4 v to 15 v 80 95 db ?40c < t a < +125c 74 db supply current per amplifier i sy ada4622 - 1 650 700 a ?40c < t a < +125c 725 a ada4622 -2 600 650 a ?40c < t a < +125c 675 a shutdown current ada4622 -1 only 50 a dynamic performance slew rate sr v out = 0.5 v to 3.5 v, r l = 2 k?, c l = 100 p f, a v = 1 low to high transition 20 v/s high to low transition ?15 v/s gain bandwidth product gbp a v = 100, c l = 35 pf 7.2 mhz unity - gain crossover ugc a v = 1 6 mhz ?3 db bandwidth ?3 db a v = 1 9 mhz phase margin m 50 degrees settling time t s v in = 4 v step, r l = 2 k ? , c l = 15 pf, a v = ?1 to 0.1% 1.5 s to 0.01% 2.0 s emi rejection ratio emirr v in = 100 mv p -p f = 1000 mhz 90 db f = 2400 mhz 90 db noise performance voltage noise e n p -p 0.1 hz to 10 hz 0.75 v p -p voltage noise density e n f = 10 hz 30 nv/hz f = 100 hz 15 nv/hz f = 1 khz 12.5 nv/hz f = 10 khz 12 nv/hz current noise density i n f = 1 khz 0.8 pa/hz total harmonic distortion + noise thd + n a v = 1, f = 10 hz to 20 khz, v in = 0.5 v rms at 1 khz bw = 80 khz 0.0025 % bw = 500 khz 0.0025 % matching specifications maximum offset voltage over temperature 0.5 mv offset voltage temperature drift 2.5 v/c input bias current 0.5 5 pa crosstalk c s r l = 5 k ? , v in = 3 v p -p f = 1 khz ?112 db f = 100 khz ?72 db
data sheet ada4622- 1/ada4622 - 2 rev. b | page 9 of 34 absolute maximum rat ings table 4 . parameter rating supply voltage 36 v input voltage ( v? ) ? 0.3 v to (v+) + 0. 2 v differential input voltage 36 v storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature, soldering (10 sec) 3 00 c esd rating , human body model (hbm) 4 kv stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. close attention to pcb thermal design is required. table 5 . thermal resistance 1 package type ja j c 2 unit 8 - lead soic 1 - layer jedec board 180 63 c/w 2 - layer jedec board 120 n/a c/w 8 - lead msop 1 - layer jedec board 265 115 c/w 2 - layer jedec board 185 n/a c/w 8 - lead lfcsp 1 - layer jedec board 272 63 c/w 2 - layer jedec board 145 n/a c/w 2 - layer jedec board with 2 2 vias 55 n/a c/w 5 - lead sot - 23 1 - layer jedec board 538 82 c/w 2 - layer jedec board 339 n/a c/w 1 thermal impedance simulated values are based on a jedec thermal test board. see jedec jesd51. 2 n/a means not applicable. esd caution
ada4622-1/ada4622-2 data sheet rev. b | page 10 of 34 pin configurations and function descriptions o ut 1 +in 3 v? 2 v+ 5 ?in 4 ada4622-1 top view (not to scale) 13502-202 figure 3. 5-lead sot-23 pin configuration, ada4622-1 table 6. 5-lead sot-23 pin function descriptions, ada4622-1 pin no. mnemonic description 1 out output 2 v? negative supply voltage 3 +in noninverting input 4 ?in inverting input 5 v+ positive supply voltage 13502-203 1 2 3 4 8 7 6 5 ada4622-1 top view (not to scale) ?in +in v? nic notes 1. nic = not interna l ly connected. v+ out nic disable figure 4. 8-lead soic pin configuration, ada4622-1 table 7. 8-lead soic pin function descriptions, ada4622-1 pin no. mnemonic description 1, 5 nic not internally connected 2 ?in inverting input 3 +in noninverting input 4 v? negative supply voltage 6 out output 7 v+ positive supply voltage 8 disable disable input (active low)
data sheet ada4622-1/ada4622-2 rev. b | page 11 of 34 1 2 3 4 ?in a +in a v? out a 8 7 6 5 out b ?in b +in b v+ 13502-101 ada4622-2 (not to scale) top view figure 5. 8-lead msop pin configuration, ada4622-2 1 2 3 4 8 7 6 5 13502-201 a da4622-2 (not to scale) top view ?in a +in a v? out a out b ?in b +in b v+ figure 6. 8-lead soic pin configuration, ada4622-2 table 8. 8-lead msop and 8-lead soic pin function descriptions, ada4622-2 pin no. mnemonic description 1 out a output, channel a 2 ?in a inverting input, channel a 3 +in a noninverting input, channel a 4 v? negative supply voltage 5 +in b noninverting input, channel b 6 ?in b inverting input, channel b 7 out b output, channel b 8 v+ positive supply voltage 13502-102 3 +in a 4 v? 1 out a notes 1. it is recommended to connect the exposed pad to the v+ pin. 2 ?in a 6?in b 5 +in b 8v+ 7out b ada4622-2 top view (not to scale) figure 7. 8-lead lfcsp pin configuration, ada4622-2 table 9. 8-lead lfcsp pin function descriptions, ada4622-2 pin no. mnemonic description 1 out a output, channel a. 2 ?in a inverting input, channel a. 3 +in a noninverting input, channel a. 4 v? negative supply voltage. 5 +in b noninverting input, channel b. 6 ?in b inverting input, channel b. 7 out b output, channel b. 8 v+ positive supply voltage. epad exposed pad. it is recommended to connect the exposed pad to the v+ pin.
ada4622-1/ada4622-2 data sheet rev. b | page 12 of 34 typical performance characteristics t a = 25c, unless otherwise noted. number of amplifiers v os (mv) v cm = 0v v out = 0v v sy = 15v 13502-002 figure 8. input offset voltage (v os ) distribution, v sy = 15 v number of amplifiers v os (mv) v cm = 0v v out = 0v v sy = 5v 13502-003 figure 9. input offset voltage (v os ) distribution, v sy = 5 v number of amplifiers v os (mv) v cm = 0v v out = 2.5v v sy = 5v 13502-004 figure 10. input offset voltage (v os ) distribution, v sy = 5 v 13502-011 ?10.0 ?7.5 ?5.0 ?2.5 0 2.5 5.0 7.5 10.0 number of amplifiers tcv os (v/c) v sy = 15v figure 11. input offset voltage drift (tcv os ) distribution (?40c to +85c), v sy = 15 v 13502-012 ?10.0 ?7.5 ?5.0 ?2.5 0 2.5 5.0 7.5 10.0 tcv os (v/c) number of amplifiers v sy = 5v figure 12. input offset voltage drift (tcv os ) distribution (?40c to +125c), v sy = 5 v 13502-013 ?10.0 ?7.5 ?5.0 ?2.5 0 2.5 5.0 7.5 10.0 tcvos (v/c) number of amplifiers v sy = 5v figure 13. input offset voltage drift (tcv os ) distribution (?40c to +125c), v sy = 5 v
data sheet ada4622-1/ada4622-2 rev. b | page 13 of 34 ?1000 ?500 0 500 1000 ?15 ?10 ?5 0 5 10 15 v os (v) v cm (v) 13502-008 v sy = 15v figure 14. input offset voltage (v os ) vs. common-mode voltage (v cm ), v sy = 15 v ?1000 ?500 0 500 1000 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v os (v) v cm (v) 13502-009 v sy = 5v figure 15. input offset voltage (v os ) vs. common-mode voltage (v cm ), v sy = 5 v ?1000 ?500 0 500 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v os (v) v cm (v) 13502-010 v sy = 5v figure 16. input offset voltage (v os ) vs. common-mode voltage (v cm ), v sy = 5 v number of amplifiers i b (pa) v cm = 0v v out = 0v 13502-014 v sy = 15v figure 17. input bias current (i b ) distribution, v sy = 15 v i b (pa) number of amplifiers v cm = 0v v out = 0v v sy = 5v 13502-015 figure 18. input bias current (i b ) distribution, v sy = 5 v number of amplifiers i b (pa) v cm = 0v v sy = 5v v out = 2.5v 13502-016 figure 19. input bias current (i b ) distribution, v sy = 5 v
ada4622-1/ada4622-2 data sheet rev. b | page 14 of 34 ?30 ?20 ?10 0 10 ?15 ?10 ?5 0 5 10 15 i b (pa) v cm (v) v sy = 15v 13502-017 figure 20. input bias current (i b ) vs. input common-mode voltage (v cm ), v sy = 15 v ?6 ?4 ?2 0 2 4 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 i b (pa) v cm (v) v sy = 5v 13502-018 figure 21. input bias current (i b ) vs. input common-mode voltage (v cm ), v sy = 5 v 0 0.51.01.52.02.53.03.54.04.55.0 i b (pa) v cm (v) v sy = 5v 13502-019 figure 22. input bias current (i b ) vs. input common-mode voltage (v cm ), v sy = 5 v v ol (v) i load (a) ?40c +25c +85c +125c v sy = 15v 13502-020 figure 23. output voltage low (v ol ) to supply rail vs. load current (i load ) over temperature, v sy = 15 v v ol (v) i load (a) ?40c +25c +85c +125c v sy = 5v 13502-021 figure 24. output voltage low (v ol ) to supply rail vs. load current (i load ) over temperature, v sy = 5 v v ol (v) i load (a) ?40c +25c +85c +125c v sy = 5v 13502-022 figure 25. output voltage low (v ol ) to supply rail vs. load current (i load ) over temperature, v sy = 5 v
data sheet ada4622-1/ada4622-2 rev. b | page 15 of 34 v oh (v) i load (a) ?40c +25c +85c +125c v sy = 15v 13502-023 figure 26. output voltage high (v oh ) to supply rail vs. load current (i load ) over temperature, v sy = 15 v v ol (v) i load (a) ?40c +25c +85c +125c v sy = 5v 13502-024 figure 27. output voltage high (v oh ) to supply rail vs. load current (i load ) over temperature, v sy = 5 v v ol (v) i load (a) ?40c +25c +85c +125c v sy = 5v 13502-025 figure 28. output voltage high (v oh ) to supply rail vs. load current (i load ) over temperature, v sy = 5 v gain (db) load resistance (k ? ) v sy = 5v v sy = 5v v sy = 15v 13502-026 figure 29. open-loop gain (a vo ) vs. load resistance ?135 ?90 ?45 0 45 90 135 180 225 ?40 ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m phase (degrees) gain (db) frequency (hz) v sy = 15v 13502-027 figure 30. open-loop gain and phase vs. frequency, v sy = 15 v ?135 ?90 ?45 0 45 90 135 180 225 ?40 ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m phase (degrees) gain (db) frequency (hz) v sy = 5v 13502-028 figure 31. open-loop gain and phase vs. frequency, v sy = 5 v
ada4622-1/ada4622-2 data sheet rev. b | page 16 of 34 ?135 ?90 ?45 0 45 90 135 180 225 ?40 ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m phase (degrees) gain (db) frequency (hz) v sy = 5v 13502-029 figure 32. open-loop gain and phase vs. frequency, v sy = 5 v ?20 ?10 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) v sy = 15v a v = +100 a v = +10 a v = +1 13502-030 figure 33. closed-loop gain vs. frequency, v sy = 15 v ?20 ?10 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) v sy = 5v a v = +100 a v = +10 a v = +1 13502-031 figure 34. closed-loop gain vs. frequency, v sy = 5 v ?20 ?10 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) v sy = 5v a v = +100 a v = +10 a v = +1 13502-032 figure 35. closed-loop gain vs. frequency, v sy = 5 v 0.01 0.1 1 10 100 1000 10 100 1k 10k 100k 1m 10m output impedance ( ? ) frequency (hz) gain = 1 gain = 10 gain = 100 13502-033 v sy = 15v figure 36. output impe dance vs. frequency, v sy = 15 v 0.01 0.1 1 10 100 1000 10 100 1k 10k 100k 1m 10m output impedance ( ? ) frequency (hz) gain = 1 gain = 10 gain = 100 13502-034 v sy = 5v figure 37. output impe dance vs. frequency, v sy = 5 v
data sheet ada4622-1/ada4622-2 rev. b | page 17 of 34 0.01 0.1 1 10 100 1000 10 100 1k 10k 100k 1m 10m output impedance ( ? ) frequency (hz) gain = 1 gain = 10 gain = 100 13502-035 v sy = 5v figure 38. output impe dance vs. frequency, v sy = 5 v 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m cmrr (db) frequency (hz) 13502-036 v sy = 15v figure 39. cmrr vs. frequency, v sy = 15 v 0 20 40 60 80 120 100 140 10 100 1k 10k 100k 1m 10m 100m cmrr (db) frequency (hz) 13502-037 v sy = 5v figure 40. cmrr vs. frequency, v sy = 5 v 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m 100m cmrr (db) frequency (hz) 13502-038 v sy = 5v figure 41. cmrr vs. frequency, v sy = 5 v ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m psrr (db) frequency (hz) v sy = 15v 13502-039 ?psrr +psrr figure 42. psrr vs. frequency, v sy = 15 v ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m psrr (db) frequency (hz) v sy = 5v 13502-040 ?psrr +psrr figure 43. psrr vs. frequency, v sy = 5 v
ada4622-1/ada4622-2 data sheet rev. b | page 18 of 34 ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m psrr (db) frequency (hz) v sy = 5v 13502-041 ?psrr +psrr figure 44. psrr vs. frequency, v sy = 5 v 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 overshoot (%) load capacitance (pf) +os ?os 13502-042 v sy = 15v figure 45. small signal overshoot (os) vs. load capacitance, v sy = 15 v 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 overshoot (%) load capacitance (pf) +os ?os 13502-043 v sy = 5v figure 46. small signal overshoot (os) vs. load capacitance, v sy = 5 v 0 10 20 30 40 50 60 1 10 100 1000 overshoot (%) load capacitance (pf) +os ?os 13502-044 v sy = 5v figure 47. small signal overshoot (os) vs. load capacitance, v sy = 5 v ?15 ?10 ?5 0 5 10 15 012345678910 voltage (v) time (s) v sy = 15v v in = 10v 13502-045 figure 48. large signal transient response, v sy = 15 v ?4 ?2 0 2 4 012345678910 voltage (v) time (s) v sy = 5v v in = 3v 13502-046 figure 49. large signal transient response, v sy = 5 v
data sheet ada4622-1/ada4622-2 rev. b | page 19 of 34 0 1 2 3 4 012345678910 voltage (v) time (s) 13502-047 v sy = 5v v in = 0.5v to 3.5v figure 50. large signal transient response, v sy = 5 v ?3 ?2 ?1 0 1 2 3 012345678910 voltage (v) time (s) v sy = 2.5v v in = 2v 13502-048 figure 51. large signal transient response, v sy = 2.5 v ?4 ?2 0 2 4 012345678910 v o l t age (v) time (s) v sy = 15v v in = 50mv p-p 13502-049 figure 52. small signal transient response, v sy = 15 v 0 1 2 3 4 012345678910 voltage (v) time (s) v sy = 5v v in = 50mv p-p 13502-050 figure 53. small signal transient response, v sy = 5 v 0.15 0.20 0.25 0.30 0.35 012345678910 voltage (v) time (s) 13502-051 v sy = 5v v in = 0.2v to 0.3v figure 54. small signal transient response, v sy = 5 v ?20 ?10 0 10 20 ?15 ?10 ?5 0 5 012345678910 output voltage (v) input voltage (v) time (s) 13502-052 v sy = 15v figure 55. negative overload recovery, a v = ?10, v sy = 15 v
ada4622-1/ada4622-2 data sheet rev. b | page 20 of 34 ?6 ?3 0 3 6 ?3 ?2 ?1 0 1 012345678910 output voltage (v) input voltage (v) time (s) 13502-053 v sy = 5v figure 56. negative overload recovery, a v = ?10, v sy = 5 v ?3 ?2 ?1 1 0 2 ?2.0 ?1.5 ?1.0 0 ?0.5 0.5 012345678910 output voltage (v) input voltage (v) time (s) 13502-054 v sy = 2.5v figure 57. negative overload recovery, a v = ?10, v sy = 2.5 v ?5 5 15 25 35 ?15 ?10 ?5 0 5 012345678910 output voltage (v) input voltage (v) time (s) 13502-055 v sy = 15v figure 58. positive overload recovery, a v = ?10, v sy = 15 v ?3 0 3 9 6 12 ?4 ?3 ?2 0 ?1 1 012345678910 output voltage (v) input voltage (v) time (s) 13502-056 v sy = 5v figure 59. positive overload recovery, a v = ?10, v sy = 5 v ?1 1 0 2 4 3 5 ?2.5 ?2.0 ?1.5 0 ?0.5 ?1.0 0.5 012345678910 output voltage (v) input voltage (v) time (s) 13502-057 v sy = 2.5v figure 60. positive overload recovery, a v = ?10, v sy = 2.5 v 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 ?25 ?20 ?15 ?10 -5 0 5 10 012345678910 output voltage (v) input v o ltage (v) time (s) v sy = 15v v in = 5v 13502-058 figure 61. positive settling time, a v = ?10, v sy = 15 v
data sheet ada4622-1/ada4622-2 rev. b | page 21 of 34 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 ?20 ?16 ?12 ?8 ?4 0 4 8 012345678910 output voltage (v) input voltage (v) time (s) v sy = 5v v in = 4v 13502-059 figure 62. positive settling time, a v = ?10, v sy = 5 v ?0.01 0.01 0 0.02 0.04 0.03 0.05 ?12 ?10 ?8 ?2 ?4 ?6 0 012345678910 output voltage (v) input voltage (v) time (s) 13502-060 v sy = 5v v in = ?0.5v to ?4.5v figure 63. positive settling time, a v = ?10, v sy = 5 v ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ? 0.01 ?25 ?20 ?15 ?10 ?5 0 5 10 012345678910 output voltage (v) input v o ltage (v) time (s) v sy = 15v v in = 5v 13502-061 figure 64. negative setting time, a v = ?10, v sy = 15 v ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 ?20 ?16 ?12 ?8 ?4 0 4 80 012345678910 output voltage (v) input voltage (v) time (s) v sy = 5v v in = 4v 13502-062 figure 65. negative setting time, a v = ?10, v sy = 5 v ?0.04 ?0.02 ?0.03 ?0.01 0.01 0 0.02 ?12 ?10 ?8 ?2 ?4 ?6 0 012345678910 output voltage (v) input voltage (v) time (s) 13502-063 v sy = 5v v in = ?0.5v to ?4.5v figure 66. negative setting time, a v = ?10, v sy = 5 v v o ltage noise density (nv/ 13502-064 frequency (hz) v sy = 15v figure 67. voltage noise density, v sy = 15 v
ada4622-1/ada4622-2 data sheet rev. b | page 22 of 34 13502-065 ch1 200mv m1.00ms a ch1 ?3.80mv 1 ch1 p-p = 776.0mv v sy = 15v figure 68. 0.1 hz to 10 hz noise, v sy = 15 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 2 4 6 8 10 12 14 16 18 supply current (ma) supply voltage (v) ?40c +25c +85c +125c 13502-066 figure 69. supply current (i sy ) vs. supply voltage (v sy ) for various temperatures 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 supply current (ma) temperature (c) v sy = +5v v sy = 2.5v v sy = 5v v sy = 15v 13502-067 figure 70. supply current (i sy ) vs. temperature for various supply voltages ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channel separation (db) frequency (hz) v sy = 15v v in = 20v p-p 13502-068 figure 71. channel separation vs. frequency, v sy = 15 v 0.0001 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) amplitude (v rms) v sy = 15v bw = 500khz bw = 80khz 13502-069 figure 72. thd + n vs. amplitude, v sy = 15 v 0.0001 0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 thd + n (%) amplitude (v rms) v sy = 5v bw = 500khz bw = 80khz 13502-070 0.001 figure 73. thd + n vs. amplitude, v sy = 5 v
data sheet ada4622-1/ada4622-2 rev. b | page 23 of 34 0.0001 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) amplitude (v rms) v sy = 5v bw = 500khz bw = 80khz 13502-071 figure 74. thd + n vs. amplitude, v sy = 5 v 0.00001 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k thd + n (%) frequency (hz) v sy = 15v bw = 500khz bw = 80khz 13502-072 figure 75. thd + n vs. frequency, v sy = 15 v 0.00001 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k thd + n (%) frequency (hz) v sy = 5v bw = 500khz bw = 80khz 13502-073 figure 76. thd + n vs. frequency, v sy = 5 v 0.001 0.01 0.1 10 100 1k 10k 100k thd + n (%) frequency (hz) v sy = 5v bw = 500khz bw = 80khz 13502-074 figure 77. thd + n vs. frequency, v sy = 5 v 0 10 20 30 40 50 60 70 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 shutdown current (a) temperature (c) 15v 5v +5v 13502-277 figure 78. shutdown current vs. temperature
ada4622-1/ada4622-2 data sheet rev. b | page 24 of 34 theory of operation slew enhancement circuit ed1 +in x v? out x v+ ? in x ed2 r1 r3 r4 r8 r9 r10 r7 q1 q3 c1 q2 q4 q5 rr output stage v bias r5 r6 in out1 out2 j2 j1 r2 ed3 ed4 ed5 ed6 imagic current current mirror 13502-075 figure 79. simplified circuit diagram input characteristics the ada4622-1 / ada4622-2 input stage consists of n-channel, jfets that provide low offset, low noise, and high impedance. the minimum input common-mode voltage extends from ?0.2 mv below v? to 1 v less than v+. driving the input closer to the positive rail causes loss of amplifier bandwidth and increased common-mode voltage error. figure 80 shows the rounding of the output due to the loss of bandwidth. the input and output are superimposed. 13502-076 ch1 1.00v ch2 1.00v m2.00s a ch1 3.00v 1 figure 80. bandwidth limiting due to headroom requirements the ada4622-1 / ada4622-2 do not exhibit phase reversal for input voltages up to v+. for input voltages greater than v+, a 10 k resistor in series with the noninverting input prevents phase reversal at the expense of higher noise (see figure 81). 13502-077 ch1 1.00v ch2 1.00v m2.00s 1 a ch1 3.84v figure 81. no phase reversal because the input stage uses n-channel jfets, the input current during normal operation is negative. however, the input bias current changes direction as the input voltage approaches v+ due to internal junctions becoming forward-biased (see figure 82). ?3 ?2 ?1 0 1 2 3 4 ?5?4?3?2?1012345 input bias current (pa) common-mode voltage (v) 13502-078 figure 82. input bias current vs. common-mode voltage with 5 v supply
data sheet ada4622-1/ada4622-2 rev. b | page 25 of 34 the ada4622-1 / ada4622-2 are designed for 12 nv/hz wideband input voltage noise density and maintain low noise performance at low frequencies (see figure 83). this noise performance, along with the low input current as well as low current noise, means that the ada4622-1 / ada4622-2 contribute negligible noise for applications with a source resistance greater than 10 k and at signal bandwidths greater than 1 khz. 1k 10k 100k resistance ( ? ) frequency (hz) 13502-079 ada4622-1/ada4622-2 voltage and current noise r s noise total noise figure 83. total noise vs. source resistance input overvoltage protection the ada4622-1 / ada4622-2 have internal protective circuitry that allows voltages as high as 0.3 v beyond the supplies applied at the input of either terminal without causing damage. use a current-limiting resistor in series with the input of the ada4622-1 / ada4622-2 if the input voltage exceeds 0.3 v beyond the supply rails of the amplifiers. if the overvoltage condition persists for more than a few seconds, damage to the amplifiers can result. for higher input voltages, determine the resistor value by ma10 ? ? s sy in r vv where: v in is the input voltage. v sy is the voltage of either the v+ pin or the v? pin. r s is the series resistor. with a very low input bias current of 1.5 na maximum up to 125c, higher resistor values can be used in series with the inputs without introducing large offset errors. a 1 k series resistor allows the ada4622-1 / ada4622-2 to withstand 10 v of continuous overvoltage and increases the noise by a negligible amount. a 5 k resistor protects the inputs from voltages as high as 25 v beyond the supplies and adds less than 10 v to the offset voltage of the amplifiers. emi rejection ratio figure 84 shows the emi rejection ratio (emirr) vs. the frequency for the ada4622-1 / ada4622-2 . 0 20 40 60 80 100 emirr (db) frequency (hz) competitor 1 competitor 2 ada4622-1/ada4622-2 13502-080 figure 84. emirr vs. frequency output characteristics the ada4622-1 / ada4622-2 unique bipolar rail-to-rail output stage swings within 10 mv of the supplies with no external resistive load. the ada4622-1 / ada4622-2 approximate output saturation resistance is 24 , sourcing or sinking. use the output impedance to estimate the output saturation voltage when driving heavier loads. as an example, when driving 5 ma, the saturation voltage from either rail is roughly 120 mv. if the ada4622-1 / ada4622-2 output drives hard against the output saturation voltage, it recovers within 1.2 s of the input, returning to the linear operating region of the amplifier (see figure 55 and figure 58). capacitive load drive capability direct capacitive loads interact with the effective output impedance of the ada4622-1 / ada4622-2 to form an additional pole in the feedback loop of the amplifiers, which causes excessive peaking on the pulse response or loss of stability. the worst case condition is when the devices use a single 5 v supply in a unity- gain configuration. figure 85 shows the pulse response of the ada4622-1 / ada4622-2 driving 500 pf directly. 13502-081 ch1 50.0mv b w m2.00s a ch1 108mv 1 figure 85. pulse response with 500 pf load capacitance
ada4622-1/ada4622-2 data sheet rev. b | page 26 of 34 shutdown operation use the active low disable input to put the ada4622-1 into shutdown mode. when the voltage on the disable input is less than 1.4 v above the negative supply voltage (v?), the ada4622-1 shuts down and consumes only 50 a to 60 a typical. when the voltage on the disable input is more than 1.4 v above the negative supply voltage (v?), or if the disable input is left floating, the ada4622-1 powers up. for best performance, it is recommended that the input voltage level on the disable input be v? or that the input be left floating. the ada4622-1 is still a drop-in replacement for devices with standard single channel op-amp pinouts because the ada4622-1 enables when the disable input is left floating. figure 86 shows a simplified circuit for the disable input. disable mirror i out 13502-285 figure 86. simplified circuit for the disable input figure 87 and figure 88 show the start-up and shutdown response when toggling the disable input. ch1 50mv ch2 5v m1.00s a ch2 ?11.5v 1 1 t 49.8% ? : 1.12s ? : 5mv @: 1.10s @: ?1mv 13502-286 figure 87. start-up response when toggling the disable input ch1 100mv ch2 5v m1.00s a ch2 ?11.5v 1 1 t 49.8% ? : 1.98s ? : 2mv @: ?60ns @: 2mv 13502-287 figure 88. shutdown response when toggling the disable input figure 89 shows the disable input current vs. the disable input voltage relative to the negative supply voltage (v?). disable input current (a) 0123 disable input voltage relative to v? (v) 456 13502-288 figure 89. disable input current vs. disable input voltage relative to v?
data sheet ada4622-1/ada4622-2 rev. b | page 27 of 34 applications information recommended power solution the ada4622-1 / ada4622-2 can operate from a 2.5 v to 15 v dual supply or a 5 v to 30 v single supply. the adp7118 and the adp7182 are recommended to generate the clean positive and negative rails for the ada4622-1 / ada4622-2 . both low dropout regulators (ldos) are available in fixed output voltage or adjustable output voltage versions. to generate the input voltages for the ldos, the adp5070 dc-to-dc switching regulator is recommended. figure 90 shows the recommended power solution configuration for the ada4622-1 / ada4622-2 . adp5070 adp7118 adp7182 +12v +16v +15v ?15v ?16v 13502-082 figure 90. power solution configuration for the ada4622-1 / ada4622-2 table 10. recommended power management devices product description adp5070 dc-to-dc switching regulator with independent positive and negative outputs adp7118 20 v, 200 ma, low noise, cmos ldo regulator adp7182 ?28 v, ?200 ma, low noise, linear regulator maximum power dissipation the maximum power the ada4622-1 / ada4622-2 can safely dissipate is limited by the associated rise in junction temperature. for plastic packages, the maximum safe junction temperature is 150c. if this maximum temperature is exceeded, reduce the die temperature to restore proper circuit operation. leaving the device in the overheated condition for an extended period can result in device burnout. to ensure proper operation, it is important to observe the absolute maximum ratings and thermal resistance specifications. second-order low-pass filter figure 91 shows the ada4622-1 / ada4622-2 configured as a second-order, butterworth, low-pass filter. with the values as shown, the corner frequency equals 200 khz. the following equations show the component selection: r1 = r2 = user selected (typical values: 10 k to 100 k) r1f c1 cutoff ? ? 2 1.414 r1f c cutoff ? ? 2 0.707 2 ada4622-1/ ada4622-2 c3 0.1f +5v c4 0.1f v out v in c1 28pf ?5v c2 56pf r1 20k ? r2 20k ? 50pf 13502-083 figure 91. second-order, butterworth, low-pass filter figure 92 shows a plot of the filter; greater than 35 db of high frequency rejection is achieved. 100 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 1k 10k 100k frequency (hz) 1m 10m 100m 13502-084 amplitude (db) figure 92. frequency response of the filter wideband photodiode preamplifier the ada4622-1 / ada4622-2 are an excellent choice for photodiode preamplifier applications. the low input bias current minimizes the dc error at the output of the preamplifier. in addition, the high gain bandwidth product and low input capacitance maximizes the signal bandwidth of the photodiode preamplifier. figure 93 shows the ada4622-1 / ada4622-2 as a current to voltage (i to v) converter with an electrical model of a photodiode. ? + v out v b c d c m c m r sh = 10 11 ? c s i photo c f r f 13502-085 ada4622-1/ ada4622-2 figure 93. wideband photodiode preamplifier
ada4622-1/ada4622-2 data sheet rev. b | page 28 of 34 the following basic transfer function describes the transimpedance gain of the photodiode preamplifier: f f f photo out r sc r i v ? ? ? 1 where i photo is the output current of the photodiode. the parallel combination of r f and c f sets the signal bandwidth (see the i to v gain curve in figure 95). s refers to the s-plane. note that r f must be set so the maximum attainable output voltage corresponds to the maximum diode output current, i photo , which allows use of the full output swing. the attainable signal bandwidth with this photodiode preamplifier is a function of r f , the gain bandwidth product (f gbp ) of the amplifier, and the total capacitance at the amplifier summing junction, including c s and the amplifier input capacitance, c d and c m . r f and the total capacitance produce a pole with loop frequency (f p ). s f p c r f ? ? 2 1 with the additional pole from the amplifier open-loop response, the two-pole system results in peaking and instability due to an insufficient phase margin (see figure 94). log f log f g = 1 g = r2c1s open-loop gain phase () |a| (db) ?180 ?135 ?90 ?45 0 13502-086 f p f x f gbp figure 94. gain and phase plot of the transimpedance amplifier design, without compensation open-loop gain f f p g = 1 f f gbp g = 1 + c s /c f f z f x f n i to v gain |a (s)| ? 135 ?90 ?45 0 45 90 g = r f c s (s) 13502-087 figure 95. gain and phase plot of the transimpedance amplifier design with compensation adding c f creates a zero in the loop transmission that compensates for the effect of the input pole, which stabilizes the photodiode preamplifier design because of the increased phase margin. adding c f also sets the signal bandwidth (see figure 95). the signal bandwidth and the zero frequency are determined by f f z c r f 2 1 ? where f z is the zero frequency. setting the zero at the f x frequency maximizes the signal bandwidth with a 45 phase margin. because f x is the geometric mean of f p and f gbp , it can be calculated by gbp p x f f f ? ? combining these equations, the c f value that produces f x is gbp f s f f r c c ? ? ? ? 2 the frequency response in this case shows about 2 db of peaking and 15% overshoot. doubling c f and halving the bandwidth results in a flat frequency response with about 5% transient overshoot. the dominant sources of output noise in the wideband photodiode preamp design are the input voltage noise of the amplifier, v noise , and the resistor noise due to r f . the gray curve in figure 95 shows the noise gain over frequencies for the photodiode preamp.
data sheet ada4622-1/ada4622-2 rev. b | page 29 of 34 calculate the noise bandwidth at the f n frequency by ff s gbp n ccc f f )( ? ? figure 96 shows the ada4622-1 / ada4622-2 configured as a transimpedance photodiode amplifier. the amplifiers are used in conjunction with a photodiode detector with an input capacitance of 5 pf. figure 97 shows the transimpedance response of the ada4622-1 / ada4622-2 when i photo is 1 a p-p. the amplifiers have a bandwidth of 2 mhz when they are maximized for a 45 phase margin with c f = 2 pf. note that with the pcb parasitics added to c f , the peaking is only 0.5 db, and the bandwidth is reduced slightly. increasing c f to 3 pf completely eliminates the peaking; however, increasing c f to 3 pf reduces the bandwidth to 1 mhz. table 11 shows the noise sources and total output noise for the photodiode preamp, where the preamp is configured to have a 45 phase margin for maximum bandwidth and f z = f x = f n in this case. 0.1f +5v 49.9k ? v out 0.1f ?5v ? 5 v 100 ? 2pf 13502-088 ada4622-1/ ada4622-2 figure 96. photodiode preamplifier 10 100 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 1k 10k 100k frequency (hz) amplitude (db) 1m 10m 100m 13502-089 2pf 3pf figure 97. photodiode preamplifier frequency response table 11. rms noise contributions of the photodiode preamplifier contributor expression rms noise (v) 1 r f 2 ??? nf fr4kt 50.8 v noise n f dfm s noise f c cccc v ? ? ? ??? ? 2 ) ( 131.6 root sum square (rss) total 2 2 noise f vr ? 141 1 rms noise with r f = 50 k, c s = 5 pf, c f = 2 pf, c m = 3.7 pf, and c d = 0.4 pf.
ada4622-1/ada4622-2 data sheet rev. b | page 30 of 34 peak detector a peak detector captures the peak value of a signal and produces an output equal to it. by taking advantage of the dc precision and super low input bias current of the jfet input amplifiers, such as the ada4622-1 / ada4622-2 , a highly accurate peak detector can be built, as shown in figure 98. ada4622-1/ ada4622-2 ada4622-1/ ada4622-2 v cc v cc v in + ? v ee v ee u1 3 2 4 8 1 5 6 4 8 7 c4 50pf c3 1f r6 1k? r7 10k ? d2 1n448 d3 1n4148 +peak d4 1n4148 u2 13502-090 figure 98. positive peak detector in this application, d3 and d4 act as unidirectional current switches that open when the output is kept constant in hold mode. to detect a positive peak, u2a drives c3 through d3 and drives d4 until c3 is charged to a voltage equal to the input peak value. feedback from the output of the u2b (positive peak) through r6 limits the output voltage of u2a. after detecting the peak, the output of u2a swings low but is clamped by d2. d3 reverses bias and the common node of d3, d4, and r7 is held to a voltage equal to positive peak by r7. the voltage across d4 is 0 v; therefore, the leakage is small. the bias current of u2b is also small. with almost no leakage, c3 has a long hold time. the ada4622-1 / ada4622-2 , shown in figure 98, are a perfect fit for building a peak detector because u1 requires dc precision and high output current during fast peaks, and u2 requires low input bias current (i b ) to minimize capacitance discharge between peaks. a low leakage and low dielectric absorption capacitor, such as polystyrene or polypropylene, is required for c3. reversing the diode directions causes the circuit to detect negative peaks. multiplexing inputs by using the ada4622-1 disable input, it is possible to multiplex two inputs to a single output by using the circuit shown in figure 99. if the gain configuration or filter configuration of the two amplifiers is different, and a common single input to both amplifiers is used, this configuration can control selectable gain or selectable frequency response at the output. v + v + ? ada4622-1 ada4622-1 v? u1 3 2 4 7 6 8 vout v v + ? v? u2 3 2 4 7 6 8 disable 13502-298 figure 99. multiplexed input circuit figure 100 shows the output response when multiplexing two input signals. the input to the first amplifier is a 4 v p-p, 200 khz sine wave; the input to the second amplifier is an 8 v p-p, 100 khz sine wave. output v logic time vol t age 13502-299 figure 100. multiplexed output
data sheet ada4622-1/ada4622-2 rev. b | page 31 of 34 full wave rectifier figure 101 shows the circuit of a full-wave rectifier using two ada4622-1 op amps in single-supply operation. the circuit is composed of a voltage follower (u1) and a second stage amplifier (u2) that combine the output of the first stage amplifier and the inverted version of the input signal. u1 follows the input during the positive half cycle and clamps the negative going input signal to ground giving a half wave signal at v hw . the following equation defines the circuit transfer function: v fw = (1+ r3 / r2 ) v hw ? ( r3 / r2 ) v in where: v fw is the full wave output from u1. r3 and r2 are the feedback resistors shown in figure 101. v hw is half wave output from u1. v in is the input voltage. 2v p-p 1khz 0 r1 30k? v fw u1 u2 v cc 5v v cc 5v gnd gnd gnd r2 50k ? r3 50k ? 13502-300 figure 101. full wave rectifier circuit during the input positive half cycle, u1 follows the input so that v hw = v in ; therefore, v fw = v in . during the negative half cycle, u1 clamps the signal to ground so that v hw = 0 v; therefore, v fw = ?(r3/r2) v in = ?v in because r3/r2 = 1. figure 102 shows the input and outputs waveforms from the circuit. the input is 2 v p-p, 1 khz sine wave while the circuit is running on a 5 v single supply. input half wave full wave 13502-301 time vol t age figure 102. full wave and half wave rectifier input and output waveforms
ada4622-1/ada4622-2 data sheet rev. b | page 32 of 34 outline dimensions compliant to jedec standards mo-178-aa 10 5 0 seating plane 1.90 bsc 0.95 bsc 0.60 bsc 5 123 4 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.20 max 0.08 min 0.50 max 0.35 min 0.55 0.45 0.35 11-01-2010-a figure 103. 5-lead small outline transistor package [sot-23] (rj-5) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 104. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
data sheet ada4622-1/ada4622-2 rev. b | page 33 of 34 8 1 5 4 0.30 0.25 0.20 pin 1 index area seating plane 0.80 0.75 0.70 1.55 1.45 1.35 1.84 1.74 1.64 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed-4 05-11-2016-a p i n 1 i n d i c a t o r ( r 0 . 1 5 ) top view bottom view side view figure 105. 8-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp-8-13) dimensions shown in millimeters compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 106. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ada4622-1/ada4622-2 data sheet rev. b | page 34 of 34 ordering guide model 1 temperature range package description package option branding ADA4622-1ARJZ-R2 ?40c to +125c 5-lead small outline transistor package [sot-23] rj-5 a3j ada4622-1arjz-r7 ?40c to +125c 5-lead small o utline transistor package [sot-23] rj-5 a3j ada4622-1arjz-rl ?40c to +125c 5-lead small o utline transistor package [sot-23] rj-5 a3j ada4622-1arz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-1arz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-1arz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-1brz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-1brz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-1brz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-2acpz-r7 ?40c to +125c 8-lead lead frame chip scale package [lfcsp] cp-8-13 a3d ada4622-2acpz-rl ?40c to +125c 8-lead lead frame chip scale package [lfcsp] cp-8-13 a3d ada4622-2armz ?40c to +125c 8-lead mini small outline package [msop] rm-8 a3d ada4622-2armz-r7 ?40c to +125c 8-lead mini small outline package [msop] rm-8 a3d ada4622-2armz-rl ?40c to +125c 8-lead mini small outline package [msop] rm-8 a3d ada4622-2arz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-2arz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-2arz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-2brz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-2brz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4622-2brz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 1 z = rohs compliant part. ?2015C2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13502-0-2/17(b)

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